The present invention relates to a semiconductor device and a manufacturing method therefor.
In the method for manufacturing a semiconductor device that has an MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) structure, it is one of the important elemental technologies to reduce the resistances of the diffusion layer and the gate electrode in order to cope with miniaturization and speeding-up of the semiconductor device. For the purpose of reduction in resistance, a so-called silicide technology is adopted for the semiconductor device manufacturing method, with which a low-resistance high-melting-point metal silicide is normally formed in a self-alignment manner on the surfaces of the source/drain electrodes and the gate electrode of a transistor.
The silicide technology will be specifically described below with reference to FIG. 3.
Firstly, a silicon substrate 301 including an element isolation oxide 303 and a well region 302 is prepared. Then, a gate insulator 304 is formed on the silicon substrate 301, and thereafter, a polysilicon for forming a gate electrode 305 is formed on the gate insulator 304. Then, sidewall spacers 307 are formed on both sides of the polysilicon. Subsequently, LDD (Lightly Doped Drain) regions 306 and source/drain regions 308 are formed in the well 302 by using the sidewall spacers 307 to obtain a MOSFET. Next, a high-melting-point metal (e.g., cobalt) is deposited as a film on the entire surface of the silicon substrate 301 by the sputtering method. Subsequently, heat treatment is carried out to react the high-melting-point metal with the silicon, so that silicide layers 310 are formed in a self-alignment manner on the gate electrode 305 and the source/drain regions 308. Then, unreacted high-melting-point metal is removed by chemical processing. Finally, heat treatment is carried out to make the silicide layers 310 have a low resistance.
However, during the silicidation process as described above, the silicide reaction nonuniformly progresses due to a crystal defect and so on existing in the silicon, and thereby unevenness generates at the interface between the silicide layers 310 and the silicon layer as shown in FIG. 3. As a result, the silicide layers 310 are formed partially reaching deep into the gate electrode 305 and the silicon substrate 301, disadvantageously causing obstacles in the electrical characteristics.
That is, if the silicide layer 310 reaches the neighborhood of the gate insulator 304 next to the gate electrode 305, then there are caused a change in the transistor characteristics and deterioration in the gate insulator reliability. Moreover, if the silicide layers 310 reach the neighborhood of the junction plane of the well region 302 and the source/drain region 308, then an increase in the junction leakage current is caused.
The short-channel effect of the transistor becomes significant as the semiconductor device is miniaturized and integrated in a large scale. Accordingly, there is generally adopted a method for shallowing the pn junction depth of the source/drain regions as a measure for avoiding the short-channel effect. However, there is a significant problem that the junction leakage current increases due to the nonuniformity of the silicide reaction as the pn junction depth of the source/drain regions is shallowed.
For example, JP 05-326552A discloses a method for solving the increase in the junction leakage current caused by the nonuniformity of the silicide reaction. This document proposes a method for making the source/drain regions have a two-step structure. This method extends a distance from the silicide reaction plane to the pn junction plane, and therefore, the junction leakage current is reduced. However, there is a problem that the junction leakage current cannot completely be restrained because of not eliminating the root cause of the nonuniformity of the silicide reaction. Moreover, the influence of the silicide reaction on the gate insulator is not solved yet. In other words, there is a problem that the silicide reaction cannot be blocked from reaching the gate insulator.
Moreover, JP 2002-190590A proposes a method for separating the silicide reaction plane from the source/drain region by using a selective silicon growth technique. That is, the distance between the silicide layer and the source/drain region is increased. However, there is a problem that the short-channel characteristic is deteriorated under the influence on the impurity profile of the substrate due to high-temperature heat treatment required by the selective silicon growth technique. There is a further problem that a significant increase in the number of process stages cannot be avoided.
Furthermore, JP 2001-203346A proposes a method for blocking the silicide layer from intruding into an LDD region by forming a silicide reaction blocking layer under sidewall spacers. However, an increase in the junction leakage current emerges as a problem when the pn junction depth of the source/drain region is shallowed because the silicide reaction unevenly occurs in the thickness direction of the substrate.
As described above, it is required to shallow the pn junction depth of the source/drain regions in order to block the short-channel effect in accordance with the miniaturization of the MOSFET, and it is required to form a silicide layer in order to restrain the increase in the electrical resistance of the source/drain. However, it is difficult to completely solve the problems of the junction leakage increase and the deterioration of the gate insulator reliability attributed to the nonuniform reaction of the silicide by the methods of the above-stated first through third patent documents.